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[VHDL-FPGA-Verilog] UART_VHDL_Verilog_Lattice

Description: 本压缩包中含有串口程序的VHDL,Verilog，Lattice三种版本的代码，均已实现。在压缩包中，含有非常详细的串口的实现规格。各种版本的代码中，含有完成的源文件，测试文件，模拟文件。-This compressed package contains serial process VHDL, Verilog, Lattice three versions of the code, have been achieved. In the compressed package, contains very detailed specifications of the serial implementation. Various versions of the code, containing the complete source files, test files, simulation files.
Platform: | Size: 293888 | Author: shishu | Hits:

[VHDL-FPGA-Verilog] LED_CONTROL

Description: 主要是74ls164的串行移位操作，其他的没有什么特别的地方。-Mainly 74ls164 serial shift operation, the other nothing special about it.
Platform: | Size: 1024 | Author: 张建平 | Hits:

[Other] uart_rx

Description: Tcode is in VERILOG HDL (Hardware description language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL (Hardware description language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA
Platform: | Size: 1024 | Author: hassan | Hits:

[SCM] IS61LV6416L.v

Description: ISSI 61系列门级仿真源代码 （很难找的哦）-ISSI 61 serial Verilog model
Platform: | Size: 25600 | Author: wyc | Hits:

[VHDL-FPGA-Verilog] tlc2543AND11channel

Description: 11路串行AD采集芯片TLC2543，12BIT精度输出，100Khz，采用VERILOG HDL编写，占用200个LE-11-Channel Serial AD acquisition chip TLC2543, 12BIT accuracy of the output, 100Khz, using VERILOG HDL preparation, taking up 200 LE
Platform: | Size: 32768 | Author: chenwl | Hits:

[VHDL-FPGA-Verilog] RS232

Description: RS232_串口通信的发送端verilog源程序代码-RS232_ serial communication sender verilog source code
Platform: | Size: 2048 | Author: 咕嘟大树 | Hits:

[VHDL-FPGA-Verilog] Verilog_uart

Description: 异步通讯串口调试程序，用VERILOG写的，保证能用-Asynchronous communications serial port debugger, using VERILOG written assurance can be used
Platform: | Size: 8192 | Author: xiaozhaofeng | Hits:

[VHDL-FPGA-Verilog] eda

Description: 利用FPGA可编程芯片及Verilog HDL语言实现了对直流电机PwM控制器的设计，对直流电机速度进行控制。介绍了用Verilog HDL语言编程实现直流电机PwM控制器的PwM产生模块、串口通信模块、转向调节模块等功能，该系统无须外接D／A转换器及模拟比较器，结构简单，控制精度高，有广泛的应用前景。同时，控制系统中引入上位机控制功能，可方便对电机进行远程控制。-Using FPGA programmable chip and Verilog HDL language for the design of DC motor PwM controller, DC motor speed control. Introduced with the Verilog HDL language programming controller PwM DC PwM generated module, serial communication module, steering adjustment module and other functions, the system is an external D/A converters and analog comparators, simple structure, high control precision, there a wide range of applications. Meanwhile, the introduction of PC control system control functions can be easily remote control the motor.
Platform: | Size: 4268032 | Author: 杨汉轩 | Hits:

[VHDL-FPGA-Verilog] seqdet

Description: 串行序列检测器，以得到modelsim仿真波形，用verilog编写。-Serial sequence detector to get modelsim simulation waveform, prepared with verilog.
Platform: | Size: 205824 | Author: ll | Hits:

[VHDL-FPGA-Verilog] async_uart

Description: 用verilog写的串口接收发送通信程序，已经在cyclone EP1C12Q240C8调试通过-Serial receiver with verilog send written communication procedures, has been adopted in the cyclone EP1C12Q240C8 debugging
Platform: | Size: 2375680 | Author: 莫少宁 | Hits:

[VHDL-FPGA-Verilog] serial

Description: 通过verilog 语言实现的串口通讯程序，已经压缩，无密码-Verilog language through the serial communication program, has compression, no password
Platform: | Size: 70656 | Author: 天良 | Hits:

[VHDL-FPGA-Verilog] uart_verilog

Description: UART Verilog，书中里的例子，绝对正确，用Verilog语言编写的串口通信例子-UART VerilogCommand Parsing NiosII serial serial parts, including the interruption, send the command prompt, receiving treatment and other characters. Spent a lot of hard work! Definitely useful for beginners
Platform: | Size: 4096 | Author: 李燕乐 | Hits:

[VHDL-FPGA-Verilog] 8b10b_encdec_latest[1].tar

Description: Serial peripheral interface for M68HC11 compatible
Platform: | Size: 135168 | Author: hr | Hits:

[VHDL-FPGA-Verilog] Verilog

Description: 各类verilog源代码 计数器，全加器，串行快等。-All verilog source code counter, adder, serial quick.
Platform: | Size: 21504 | Author: 王腾 | Hits:

[VHDL-FPGA-Verilog] SPI_controller

Description: SPI serial flash ROM的verilog源代码, 针对winbond W25x16,已经经过逻辑验证,并实际用在芯片设计中,作为一个模块,正常工作.-SPI serial flash ROM in verilog source code for winbond W25x16, logic has been verified, and actually used in chip design, as a module to work.
Platform: | Size: 8192 | Author: Jerd Hu | Hits:

[VHDL-FPGA-Verilog] LTC1407A

Description: LTC1407A仿真 可以模拟其全部功能 具有单端输入 时钟 串行输出-LTC1407A simulation can simulate all the functions in its single-ended input clock serial output
Platform: | Size: 1024 | Author: liu | Hits:

[VHDL-FPGA-Verilog] serial

Description: 实现了一个串口功能，用Verilog语言写的，可作为IP使用-Implements a serial port function, written using Verilog language can be used as an IP
Platform: | Size: 419840 | Author: hongfeng | Hits:

[VHDL-FPGA-Verilog] RS232

Description: 实现FPGA的RS232串行通信，采用verilog语言编写，下载到芯片上就可以使用-FPGA implementation of the RS232 serial communication, using verilog language, can be downloaded to the chip using
Platform: | Size: 600064 | Author: shineson | Hits:

[VHDL-FPGA-Verilog] SERDES

Description: 基于Verilog的串并转换器的设计与实现，采用两种不同的方案来实现串并和并串转换的功能，并用ISE软件仿真以及chipscope的调试-Verilog-based serial and parallel converter design and implementation of two different programs to achieve the string and and and string conversion functions, and use the ISE software simulation and debugging chipscope
Platform: | Size: 785408 | Author: 陈凯 | Hits:

[VHDL-FPGA-Verilog] rs232

Description: 本设计是PC和FPGA的串口通信的程序，用的是VERILOG语言，调试成功，用户可根据自己的项目稍作改动。-The design is a PC and the FPGA' s serial communication procedures, using a VERILOG language, debugged, the user can make a little change according to their own projects.
Platform: | Size: 2048 | Author: 陆景鹏 | Hits:
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